In the fabrication of integrated circuits, particularly metal-oxide-semiconductor (MOS) integrated circuits, one of the initial processing steps concerns the formation of thick field isolation regions at predetermined sites on the semiconductor substrate. Usually, the substrate is mono-crystalline silicon and the isolation regions are silicon dioxide. These thick field oxide regions are used primarily for isolation, that is, to prevent parasitic conduction which would otherwise occur when conductive lines cross these regions between active devices.
Many of the common processes for forming these field oxide regions uses a silicon nitride layer over the future active areas, i.e. the regions where devices will be built. Openings are formed in this layer at the predetermined sites where the isolating material, usually silicon dioxide is then grown on the substrate. The oxide grows primarily at the openings and not at the regions protected by the silicon nitride layer. However, as the oxide grows vertically, it encroaches horizontally and lifts the edges of the silicon nitride layer at the edges. In these areas of lifted silicon nitride, the field oxide becomes thinner, and is generally tapered. These tapered regions, which occur at the nitride-substrate interface, are sometimes called "bird's beaks" since their cross section resembles a bird's beak.
The bird's beak oxide regions consume valuable substrate area without providing benefits. For example, in the beak region of the oxide, the oxide is generally too thin to provide good field isolation and yet too thick to be used as part of active devices. A number of schemes have been proposed to reduce the bird's beak area to reclaim the silicon substrate area and increase the device density of the resulting integrated circuit chip, which is always a major concern.
For example, U.S. Pat. No. 4,111,724 shows a patterned double layer of silicon nitride over silicon oxide used as a mask for growth of isolation regions. In U.S. Pat. No. 3,783,047, a scheme is disclosed whereby a layer of oxide covered by a layer of nitride was patterned so as to over etch the oxide and thereby undercut the nitride, and thus was used as a mask to grow the field oxide.
Special treatment to the edges of the masking pattern is the subject of a number of patents. U.S. Pat. No. 4,398,992 describes a complex "Defect Free Zero Oxide Encroachment Process" using L-shaped structures of stress-relief oxide covered by nitride at the edges of the pattern to reduce bird's beak encroachment. Beveled walls of nitride-covered oxide at the edges of the field oxidation mask are shown in U.S. Pat. No. 4,533,429. And in U.S. Pat. No. 4,577,394, a mask of patterned nitride over oxide is covered by a thick layer of phosphosilicate glass (PSG) which has sloped edges that protrude beyond the edges of the nitride mask.
The well known sealed interface local oxidation (SILO) process where a patterned triple layer of two nitride layers with an oxide layer sandwiched therebetween is described by J. Hui, et al. in "Electrical Properties of MOS Devices Made with SILO Technology", Proceedings of IEDM, 1982, pp. 220-223. Thermally grown nitride or "thermal nitride" is popular in SILO-type isolation techniques because it has been found to permit less bird's beak encroachment than nitride formed in other ways, such as by low pressure chemical vapor deposition (LPCVD). See, for example, J. Hui, et al. "Selective Oxidation Technologies for High Density MOS," IEEE Electron Device Letters, Vol. EDL-2, No. 10, October 1981, pp. 244-247 and U.S. Pat. No. 4,551,910.
Another issue that has come to light recently is that nitride layers, thermally grown or otherwise, which are used as masks in future active areas where devices are to be formed, tend to damage the surface and adversely affect the performance of devices formed there after the nitride is stripped off, particularly the gate oxide integrity of MOS transistors. Defect-free surfaces in the active regions are particularly important in very large scale integration (VLSI) integrated circuits. One possible solution to this problem may be seen in U.S. Pat. No. 4,583,281 wherein silicon oxide is used to cover the center of the future active regions and LPCVD silicon nitride is present at the edge of the mask for the field oxide growth in the form of a sidewall spacer.